Typically, a computer system includes a number of integrated circuits that communicate with one another to perform system applications. Often, the computer system includes one or more host controllers and one or more electronic subsystem assemblies, such as a dual in-line memory module (DIMM), a graphics card, an audio card, a facsimile card, and a modem card. To perform system functions, the host controller(s) and subsystem assemblies communicate via communication links, such as serial communication links. Serial communication links include links that implement the fully buffered DIMM (FB-DIMM) advanced memory buffer (AMB) standard, the peripheral component interconnect express (PCIe) standard, or any other suitable serial communication link system.
An AMB chip is a key device in an FB-DIMM. An AMB has two serial links, one for upstream traffic and the other for downstream traffic, and a bus to on-board memory, such as dynamic random access memory (DRAM) in the FB-DIMM. Serial data from a host controller sent through the downstream serial link (southbound) is temporarily buffered, and can then be sent to memory in the FB-DIMM. The serial data contains the address, data, and command information given to the memory, converted in the AMB, and sent to the memory bus. The AMB writes in and reads out data from the memory as instructed by the host controller. The read data is converted to serial data, and sent back to the host controller on the upstream serial link (northbound).
An AMB also performs as a repeater between FB-DIMMs on the same channel. The AMB transfers information from a primary southbound link connected to the host controller or an upper AMB to a lower AMB in the next FB-DIMM via a secondary southbound link. The AMB receives information in the lower FB-DIMM from a secondary northbound link, and after merging the information with information of its own, sends it to the upper AMB or host controller via a primary northbound link. This forms a daisy-chain among FB-DIMMs. A key attribute of the FB-DIMM channel architecture is the high-speed, serial, point-to-point connection between the host controller and FB-DIMMs on the channel. The AMB standard is based on serial differential signaling.
PCIe is also a high-speed, serial link that communicates data via differential signal pairs. A PCIe link is built around a bidirectional, serial, point-to-point connection known as a “lane”. At the electrical level, each lane utilizes two unidirectional low voltage differential signaling pairs, a transmit pair and a receive pair, for a total of four data wires per lane. A connection between any two PCIe devices is known as a link, and is built up from a collection of one or more lanes. All PCIe devices minimally support single-lane (x1) links. Devices may optionally support wider links composed of x2, x4, x8, x12, x16, x32, or more lanes.
Typical chip-to-chip serial interfaces, such as a clock and data recovery circuit, are designed to meet the specifications of the system with respect to data transition density, jitter tolerance, and required tracking slew rate. The data transition density and jitter encountered by a clock and data recovery circuit depends upon the system data coding scheme and the quality of the connection channels. Based on the system data coding scheme and the quality of the connection channels, limits for the data transition density and jitter can be defined. Over these defined limits, the clock and data recovery circuit must be able to track a maximum defined amount of the phase slew rate.
If a system has a maximum data transition density and minimum untracked jitter distribution that provides an open loop gain that is too high in combination with the loop latency, the clock and data recovery circuit may show a cycle oscillation larger than the expected plus or minus one correction inherent in a digital control loop. If the cycle oscillation of the clock and data recovery circuit is larger than the target plus or minus one, then the phase error in sampling the data may be higher than expected and the feasible bit error rate of the interface undesireably higher.
For these and other reasons, there is a need for the present invention.